Welcome to the Verilog Tutorial
Here is a brief introduction to Verilog and its various aspects.
and_gate.v
// Code block 1
module and_gate (
input wire A,
input wire B,
output wire Y
);
assign Y = A & B;
endmodule
or_gate.v
// Code block 2
module or_gate (
input wire A,
input wire B,
output wire Y
);
assign Y = A | B;
endmodule